Training complex models requires enormous bandwidth between CPUs and GPUs.
A link can run at x16 for downstream traffic but scale down to x2 or x1 for upstream traffic if asymmetric workloads demand it. pci express base specification revision 60 pdf
For the first time in PCIe history, the standard has moved away from the traditional NRZ scheme. NRZ transmits one bit per clock cycle using two voltage levels. PAM4 transmits using four distinct voltage levels. This increases the raw data rate to 64 GT/s (gigatransfers per second) without doubling the fundamental clock frequency, which effectively doubles the bandwidth per pin with only a modest increase in signal loss. NRZ transmits one bit per clock cycle using
The bandwidth provided by PCIe 6.0 Base Specification is tailored for infrastructure-heavy deployments: The bandwidth provided by PCIe 6
A low-latency algorithm that fixes single-bit errors on the fly.
To double the data rate without requiring unsustainable increases in signal frequency—which would severely limit trace lengths on motherboards—the PCI-SIG introduced three foundational technologies into Revision 6.0. PAM4 Signaling (Pulse Amplitude Modulation 4-Level)